Unfortunately, these benefits have an extra cost in additional processes and masks. The physical structure is also much stronger, since only 3 layers are cut by the mini slit and 9 channel holes are supported between two deep slits.With a dummy channel hole and mini slit, channel hole patterning is more uniform and there is decreased loading of the channel hole CD and depth.The mini slit has a smaller CD and less space between neighboring channel holes than a larger normal slit, saving area in the bit line direction.
The introduction of a mini slit provides three benefits: With the combination of bit lines, word lines and string select lines, 1 of 9 memory cells can be exclusively addressed using the mini slit and two larger normal slits. The mini slit divides the top 3 ON stacks into 2 sides, with the left and right sides connected to separate string select lines. At the 64P and 96P process nodes, an extra mini slit process is introduced to cut the center dummy channel hole and effectively split 9 holes into 4 holes on each side. Patterning Scheme Analysis of Extra Mini SlitĪt the 32P TCAT process node, 1 of 4 memory cells can be exclusively addressed between any two slits using a combination of bitlines and wordlines. Enhancing device density without sacrificing the allowed process window is a key issue in 3D NAND process development. These narrower process windows are needed so that the downstream stair contact will precisely land on the staircase center without shorting the word line at the stair sidewall. Also, shrinking the stair CD and pitch will require a more uniform stair angle along with a much smaller CD variation in the stair etch process. With a smaller channel hole pitch and CD, the allowed process window for other processes (such as the channel hole to channel hole bridge during the etch process, or the channel hole to substrate open in both the etch and deposition processes) will become narrower. For example, if the slit pitch is reduced, the channel hole pitch must also be decreased at the same time. Unfortunately, these changes can introduce many challenges in lithography and downstream etch and gap filling processes. Traditionally, memory cell and staircase area could be reduced by decreasing the CD and pitch of the slit and stair structures.
In 3D NAND, slit pitch in the bitline direction, and stair pitch in the cross bitline direction, are two of the most important factors in determining memory cell and staircase area. The Effect of Patterning Schemes on the Process Window
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